Design Verification Engineer

In depth knowledge of HVL (Hardware verification Language) like specman ( e ) and experience in creating verification environments , eVCs and test cases using e on industry standard simulators.
Prior Experience in verifying Packet Processors , buffer managers ,DMA, QoS specific blocks is also an added advantage.
Domain Knowledge of Ethernet L2/L3 Switching concepts and deep understanding of Ethernet protocols.
Candidate should have a deeper understanding of various verification signoff processes like coverage driven methodologies , constraint random verification and can develop complete test plans based on the same.
Excellent design debug and root causing capabilities would be preferred.
Knowledge of UNIX/Linux based scripting Languages like perl , python.
In Depth understanding of VLSI verification flows also using in-circuit hardware emulators is an added advantage.
Good Communication skills , Open and Collaborative working style within large international teams.