Design verification engineer

Opening : Soc/IP Verification(DV)
Experience : 3-7 Yrs
Work location : Bangalore/Hyderabad/Noida
Job Description :
. Must have good knowledge on the verification flows
. Excellent hands-on debug skills and problem solving attitude.
. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC
. Experience of working on Functional Verification, SoC Verification, Power Management verification, UPF flow, Gate-level simulations
. Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script
. OVM/UVM Methodology knowledge and experience
. Must have good communication skills and the ability to work in a team environment.
. Preferably having experience in architecture such as x86 or ARM domain based SOCs