Rakshith V.s

As a VLSI engineer seeking to work in a dynamic environment and contribute towards the goals of the organization using my technical knowledge and skills, in a mutual beneficial way.

I have successfully completed my Masters in VLSI Design from Manipal university with 7.57 CGPA. i had worked as a intern in Tangent technolabs bangalore from July 9th 2016 to 21st May 2017. i have completed a project on Verification on Universal Memory Controller as a part of my ME degree.

Expertise: Verilog, System verilog, UVM, Digital VLSI Design, Analog VLSI Design