Salary300,000 - 720,000 INR (PA)
Job TypeFull Time
Job Location Noida,Uttar Pradesh,India


System Verilog 3G NCSIM Perl Design Verification VLSI Memory Modeling Engineer Verilog ESPCV Formal verification Scripting.
0 to 10 Years
Telecom / Internet
Functional Area
Software Development - Network Administration
Job Decription
Qualcomm CDMA Technologies, a.k.a. QCT - http:// qct/, is the world leader in wireless ICs powering the
majority of 3G & 4G devices, is the largest fabless semiconductor
in the world, and is consistently ranked near the top of Fortunes list
of 100 Best Companies to Work For. QCT is actively seeking experienced
Memory Modeling engineers for Bangalore Design Centre.
Minimum Qualifications
- Write behavioral models in Verilog/System Verilog for the different flavors of RAMs and ROMs.
- Build verification plan and verify the design including behavioral models.
- Verify Memory functionality, scan chain using TetraMAX, Formal verification using ESPCV.
Work with internal customers to understand the requirements and support
the customers on behavioral models and timing models throughout the
design cycle.
- Solid understanding of VLSI circuits and Spice simulator is expected.
- Drive and build automation with any of the scripting languages like Shell/Perl/TCL to improve the productivity and quality.
- Responsible for driving the verification flow and drive productivity & quality
Skills and Experience
- Bachelors/Masters in ECE with 3-5 years of relevant experience.
- HDL languages like Verilog, System Verilog.
- Spice simulators (Hsim, Finesim)
- HDL simulators (Modelsim, VCS, Ncsim)
- TetraMAX ATPG verification
- ESPCV Formal verification
- Scripting using Perl/shell/Tcl

Disha Career Services
Disha Career Services
Sector-63, Noida
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