EMULATION WITH PALLADIUM – PRE & POST SILICON VERIFICATION ENGINEER

REQUIREMENTS:
• Good understanding of Emulation tool and usage (Cadence -Palladium/Mentor-Veloce).
• Manual and Automated regression/test runs.
• C/C++ based Test Case development experience for Emulation & Post-Silicon.
• Hands on with few of these protocols "SPI, I2C, UART, SDIO, PCIe, AMBA, AHB, Ethernet, USB2.0/3.0, DDR2/3".
• Test Suit development with OS or Bare Metal for Emulation, Post-Silicon.
• Experience with any of CPU like ARM/MIPS/MCU/Others with Trace32 /JTAG is required.
• Scripting knowledge with any of Tcl/Python/Unix-Shell.
Good to have :
• Experience in RTL Based Builds for Emulation Platforms ( e.g In Circuit Emulation flow of Cadence Palladium).
• Use of good debugging methods on Emulation (e.g waveform analysis of trace captured) platforms.
• Hands on with lab equipment including Test pattern/traffic generator & analyzers .
• Knowledge of u-boot and other boot-loaders concept and application.
• Low level Assembly language programming skills and Board Bring up experience.